1. Field of the Invention
An embodiment of the present invention relates to the microelectronics field. More specifically, the present invention relates to integrated capacitors.
2. Discussion of the Related Art
Capacitors are components commonly used in most electronic circuits. Referring in particular to an electronic device being integrated in a chip of semiconductor material, many techniques are known for making the capacitors in the same chip wherein there are made other functional components of the integrated device, being both passive (such as resistors) and active (such as transistors).
For example, (integrated) Metal-Oxide-Metal (MOM) capacitors include two plates of conductive material (typically metal) between which there is grown a thin oxide layer of the metal (having insulating properties) to form a dielectric layer of the capacitor. The MOM capacitors are nowadays the preferred choice in many types of integrated devices for their manufacturing simplicity, even if they need particular manufacturing precautions in order not to damage the thin oxide layer.
On the contrary, (integrated) Metal-Insulator-Metal (MIM) capacitors are formed by two plates of conductive material (typically metal) between which there is deposited a layer of insulating material (for example, Silicon Nitride) to form the dielectric layer of the capacitor. The Silicon Nitride has a high dielectric constant, so that the MIM capacitors have a specific capacitance (per unit area of their plates) being greater than that of the MOM capacitors; this allows making more compact capacitors that, for the same overall capacity, occupy a lower area of the chip than the MOM capacitors do. Furthermore, the MIM capacitors allow integrating other components below them, with a further saving of area of the chip.
In a known structure of such integrated capacitors, a bottom plate is formed from a portion of a metal layer of the chip, being commonly used for distributing signals and/or power supply among functional components of the integrated device, while an upper plate is made within a protective layer (of insulating material) protecting the metal layer wherein there are made the bottom plate and the dielectric layer being formed thereon.
In order to make electrical connections of the top plate and of the bottom plate of the capacitor from a main surface of the chip, in such a structure it is necessary to form electrical connection paths (commonly known as via-holes) by opening corresponding holes (through a masking and etching operation) across the protective layer covering the top plate and bottom plate; therefore, the top plate should have a low thickness, so as to limit as much as possible (but not remove) a difference between an etch depth of the (thicker) protective layer covering the bottom plate and other portions of the metal layer being connected to corresponding functional components of the integrated device, and an etch depth of the (thinner) protective layer on the top plate. Such difference involves, during the etching operation, the high risk of perforating the top plate down to reach the dielectric layer that separates the two plates, thereby causing the breakage of the capacitor. In order to avoid such problem, it is therefore necessary to use detection systems of a checkpoint of the etching operation; however, this requires the use of highly sophisticated and expensive machines. Alternatively, it is possible to use a double masking and etching process with a consequent increase in the production cost of the capacitor and hence of the whole integrated device.
Furthermore, in the state of the art the quality of the dielectric layer is not optimal. In fact, the dielectric layer is made at relatively low process temperatures in order not to damage the bottom plate (typically not more than 400° C.). This has a negative effect on the chemical and mechanical properties of the dielectric layer, such as, for example, the planarity, with a consequent worsening of its insulating properties.